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APPROXIMATE EXPRESSION OF JITTER AMPLITUDE BY SLEW RATE IN RC-ACTIVE FILTERSGREGORIO JA; DRAKE JM; BURON AM et al.1982; IEE PROC., G; ISSN 0143-7089; GBR; DA. 1982; VOL. 129; NO 2; PP. 55-58; BIBL. 5 REF.Article

Analytical transient response of CMOS invertersKAYSSI, A. I; SAKALLAH, K. A; BURKS, T. M et al.IEEE transactions on circuits and systems. 1992, Vol 39, Num 1, pp 42-45, issn 0098-4094Article

THE USE OF CURRENT AMPLIFIERS FOR HIGH PERFORMANCE VOLTAGE APPLICATIONSALLEN PE; TERRY MB.1980; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1980; VOL. 15; NO 2; PP. 155-162; BIBL. 15 REF.Article

SLOPE DISTORTION AND AMPLIFIER DESIGNGARDE P.1977; MONITOR; NDL; DA. 1977; VOL. 38; NO 12; PP. 200-207; BIBL. 5 REF.Article

Space-rate coding in an adaptive silicon neuronHYNNA, Kai; BOAHEN, Kwabena.Neural networks. 2001, Vol 14, Num 6-7, pp 645-656, issn 0893-6080Article

Slew rate enhancement method for folded-cascode amplifiersREZAEI, M; ZHIAN-TABASY, E; ASHTIANI, S. J et al.Electronics Letters. 2008, Vol 44, Num 21, pp 1226-1228, issn 0013-5194, 3 p.Article

Optimizing the slew rate of SQUID systemXIE, F. X; HE, D. F; YANG, T et al.Physica. C. Superconductivity and its applications. 2000, Vol 341-48, pp 2719-2720, 4Conference Paper

THE MAXIMAL SLOPE OF A SINUSOID AND THE ACCURATE DIGITAL FILTERHALIJAK CA.1981; COMPUT. ELECTR. ENG.; ISSN 0045-7906; USA; DA. 1981; VOL. 8; NO 3; PP. 187-191; BIBL. 5 REF.Article

Frequency driven repeater insertion for deep submicronAHMED, N; TEHRANIPOUR, M. H; ZHOU, D et al.IEEE International Symposium on Circuits and Systems. 2004, pp 181-184, isbn 0-7803-8251-X, 4 p.Conference Paper

High slew-rate voltage follower based on double-sided dynamic biasingWONG, M. J; HO, M; LEUNG, K. N et al.Electronics letters. 2010, Vol 46, Num 12, pp 824-825, issn 0013-5194, 2 p.Article

Highly reproducible state-of-the-art quartz oscillatorsBLOCH, M; HO, J; MANCINI, O et al.IEEE international frequency control symposium. 2002, pp 615-618, isbn 0-7803-7082-1, 4 p.Conference Paper

CMOS amplifier design methodology for optimum slew rateFARAG, Fathi A.IEEE Mediterranean electrotechnical conference. 2002, pp 532-536, isbn 0-7803-7527-0, 5 p.Conference Paper

Slew rate enhancement via excessive transient feedbackHUANG, B; XU, L; CHEN, D et al.Electronics letters. 2013, Vol 49, Num 15, pp 930-932, issn 0013-5194, 3 p.Article

An output impedance-based design of voltage regulator output capacitors for high slew-rate load current transientsJIA WEI; LEE, Fred C.IEEE Applied Power Electronics Conference and Exposition. 2004, isbn 0-7803-8269-2, 3Vol, vol1, 304-310Conference Paper

CONTRIBUTION A L'ETUDE DE LA DYNAMIQUE DES AMPLIFICATEURS OPERATIONNELS ET DES FILTRES ACTIFSZOUELFOUKKAR ABD ELMIGID MOHAMED.1980; ; FRA; DA. 1980; 294 P.; 30 CM; BIBL. 27 REF.; TH. DOCT.-ING./TOULOUSE, I.N.P./1980Thesis

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF designYU CAO; XUEJUE HUANG; SYLVESTER, Dennis et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 1, pp 158-162, issn 1063-8210, 5 p.Article

Slew-Rate Monitoring Circuit for On-Chip Process Variation DetectionGHOSH, Amlan; RAO, Rahul M; KIM, Jae-Joon et al.IEEE transactions on very large scale integration (VLSI) systems. 2013, Vol 21, Num 9, pp 1683-1692, issn 1063-8210, 10 p.Article

Design of Digital DROS With SFQ Up/Down Counter for Wide Dynamic Operation RangeMYOREN, Hiroaki; KIMIMOTO, Yun; TERUI, Kosuke et al.IEEE transactions on applied superconductivity. 2011, Vol 21, Num 3, pp 387-390, issn 1051-8223, 4 p., 1Conference Paper

Reduction in Reflections and Ground Bounce for Signal Line Over Slotted Power Plane Using Differential Coupled Microstrip LinesSHIUE, Guang-Hwa; WU, Ruey-Beei.IEEE transactions on advanced packaging. 2009, Vol 32, Num 3, pp 581-588, issn 1521-3323, 8 p.Article

Relationship between settling time and pole-zero placements for three-stage CMOS opampCHANDRAWAT, Uday Bhanu Singh; MISHRA, D. K.International journal of electronics. 2011, Vol 98, Num 7-9, pp 901-922, issn 0020-7217, 22 p.Article

Design procedure for two-stage CMOS opamp with optimum balancing of speed, power and noiseUDAY BHANU SINGH CHANDRAWAT; MISHRA, D. K.International journal of electronics. 2009, Vol 96, Num 11-12, pp 1145-1159, issn 0020-7217, 15 p.Article

Switch-factor based loop RLC modeling for efficient timing analysisYU CAO; XIAODONG YANG; XUEJUE HUANG et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 9, pp 1072-1078, issn 1063-8210, 7 p.Article

Passive frequency compensation for high gain-bandwidth and high slew-rate two-stage OTAMIRVAKILI, A; KOOMSON, V. J.Electronics letters. 2014, Vol 50, Num 9, pp 657-659, issn 0013-5194, 3 p.Article

Design of a fast digital Double Relaxation Oscillation SQUID (corrected)PODT, M; MIEOG, A. J; FLOKSTRA, J et al.IEEE transactions on applied superconductivity. 2001, Vol 11, Num 2, pp 4054-4057, issn 1051-8223Article

Determining the appropriate scan rate to perform cyclic polarization test on the steel bars in concretePOURSAEE, A.Electrochimica acta. 2010, Vol 55, Num 3, pp 1200-1206, issn 0013-4686, 7 p.Article

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